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DS1033 3-in-1 Low Voltage Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon timing circuit Three independent buffered delays Initial delay tolerance 1.5 ns Stable and precise over temperature and voltage Leading and trailing edge precision preserves the input symmetry Standard 8-pin DIP, 8-pin SOIC Vapor phasing, IR and wave solderable Available in Tape and Reel
PIN ASSIGNMENT
IN1 IN2 IN3 GND 1 2 3 4 8 7 6 5 VCC OUT1 OUT2 OUT3
DS1033M 8-Pin DIP See Mech. Drawings Section IN1 IN2 IN3 GND 1 2 3 4 8 7 6 5 VCC OUT1 OUT2 OUT3
DS1033Z 8-Pin SOIC (150-mil) See Mech. Drawings Section
PIN DESCRIPTION
IN1-IN3 OUT1-OUT3 NC VCC GND (Sub) - Input Signals - Output Signals - No Connection - Supply Voltage - Ground - Internal substrate connection, do not make any external connections to these pins
DESCRIPTION
The DS1033 series is a low-power +3.3 Volt version of the DS1035. It is characterized for operation over the range of 2.7V to 3.6V. The DS1033 series of delay lines have three independent logic buffered delays in a single package. It is available in a standard 8-pin DIP, 150-mil 8-pin mini-SOIC. The device features precise leading and trailing edge accuracies. It has the inherent reliability of an allsilicon delay line solution. The DS1033's nominal tolerance is 1.5 ns and an additional tolerance over temperature and voltage of 1.0 ns for the faster delays. Detailed specifications are shown in Table 1. Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972) 371-4348 for further information. 1 of 6 111799
DS1033
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH , tPHL) Table 1
DELAY PER OUTPUT (ns) (note 1) 8/8/8 10/10/10 12/12/12 15/15/15 20/20/20 25/25/25 30/30/30 INITIAL TOLERANCE (note 1) 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 2.0 ns 2.0 ns TOLERANCE OVER TEMPERATURE AND VOLTAGE (note 2) VCC=2.7V VCC=3.3V =0.3V 1.0 ns 1.5 ns 1.0 ns 1.5 ns 1.0 ns 1.5 ns 1.5 ns 2.0 ns 1.5 ns 2.5 ns 2.0 ns 3.5 ns 2.0 ns 5.0 ns
PART NUMBER DS1033-80 DS1033-10 DS1033-12 DS1033-15 DS1033-20 DS1033-25 DS1033-30
NOTES:
1. Nominal conditions are +25C and VCC=+3.3 volts. 2. Temperature range of 0C to 70C. 3. Delay accuracy is for both leading and trailing edges.
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DS1033
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1033. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution ) connected to the output. The DS1033 output taps are selected and connected to the interval counter by a VHF switch control unit. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus.
DS1033 TEST CIRCUIT Figure 2
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DS1033
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +6.0V 0C to 70C -55C to +125C 260C for 10 seconds 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Active Current High Level Input Voltage Low Level Input Voltage Input Leakage High Level Output Current Low Level Output Current SYMBOL VCC ICC VIH VIL IL IOH IOL 0VVIVCC VCC=2.7V VOH=2V VCC=2.7V VOL=0.4V VCC=3.6V Period=1s 2.0 -0.5 -1.0 TEST CONDITION MIN 2.7 TYP 3.3
(TA =0C to 70C)
MAX 3.6 25 VCC +0.5 0.8 1.0 -1.0 8 UNITS V mA V V A mA mA
AC ELECTRICAL CHARACTERISTICS
PARAMETER Period Input Pulse Width Input-to-Tap Output Delay Output Rise or Fall Time Power-up Time SYMBOL tPERIOD tWI tPLH, tPHL tOR, tOF tPU MIN 2 (tWI) 100% of Tap Delay Table 1 2.0 3.0 2.5 3.5 100 TYP MAX ns ns ns ns ns ms
(TA =+25C)
UNITS NOTES 2 2
3 4
CAPACITANCE
PARAMETER Input Capacitance SYMBOL CIN MIN TYP MAX 10 pF
(TA =+25C)
UNITS NOTES
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DS1033
Ambient Temperature: 25C =3C Supply Voltage (VCC): 3.3V =0.1V Input Pulse: High: 3.0V =0.1V Low: 0.0V =0.1V Source Impedance: 50=max. Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V. Pulse Width: 500 ns Pulse Period: 1 s Output Load Capacitance: 15 pF Output: Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on the rising and falling edges. Note: The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TEST CONDITIONS
TIMING DIAGRAM
NOTES:
1. All voltages are referenced to ground. 2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be applicationsensitive with respect to de-coupling, layout, etc. 3. VCC=3.3V =10%. 4. VCC=2.7V.
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DS1033
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI(Pulse Width): The elapsed time on the pulse between the 1.5 volt point on the leading edge and the 1.5 volt point on the trailing edge, or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge. tRISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. tPLH(Time Delay, Rising): The elapsed time between the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse. tPHL(Time Delay, Falling): The elapsed time between the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse.
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